Maintaining data bit order between a memory device such as a dynamic random access memory (DRAM), static random access memory (SRAM) or Flash device and the package to which the memory device is mounted has been irrelevant until recently. That is, the ordering of data within a memory device may be different from the order in which the data is read from or written to the package without compromising data integrity. For example, the most significant data bit at the package may not correspond to the most significant data bit at the DRAM device and vice-versa. As such, data bit order between a memory device and package is conventionally lost during memory operations such as reads and writes. The data input/output (I/O) layout or ‘footprint’ of a memory device may be selected independent of the data I/O layout of a package when data bit order is not required, thus allowing independent optimization of memory and package data I/O layouts.
Some new types of memory operations require data bit order to be preserved as data propagates between a package and memory device. One such memory operation is a DRAM register readout operation. During a register readout operation, data is read from a register included in a DRAM device and propagates through a package to another device for analysis. The register contains one or more parameters of interest written into the register by the DRAM device. The state of each parameter is indicated by one or more particular register bits. Accordingly, data bit order must be preserved as data propagates between a package and DRAM device during a register readout memory operation. Otherwise, information read from the register is useless.
One type of register readout memory operation is the status register read (SRR) method proposed by the JEDEC Solid State Technology Association (ballot number JC-42.3-05-357). During an SRR operation, one or more registers in a DRAM device are read. The proposed SRR register is at least 16 bits in width. SRR bits <3:0> indicate device ID, bits <7:4> indicate manufacturer's revision number, bits <10:8> indicate refresh rate, bit <11> indicates device width, bit <12> indicates device type, and bits <15:13> indicate device density. Accordingly, data bit order must be maintained between a DRAM device and package during an SRR memory operation. That is, the nth bit read from the SRR register must correspond to the nth data bit at the package, the n-1 SRR register bit must correspond to the n-1 package data bit, etc.
DRAM-to-package data bit ordering is conventionally forced upon the package. That is, the package data I/O layout must mate with the DRAM data I/O layout in a manner that maintains data bit order between the package and DRAM device. Electrical performance of the package is degraded and cost increases when data bit ordering constraints are placed on the package. For example, many signals may undesirably cross paths in the package, resulting in noise. Wiring traces may be longer than otherwise necessary when data bit ordering is a concern. Additional substrate levels may be required if data bit ordering cannot be maintained using fewer levels.
DRAM-to-package data bit ordering requirements become more difficult to accommodate in light of the various types of packages available for use with DRAM devices. For example, JEDEC specifies numerous types of DRAM packages such as multi-chip package (MCP), package-on-package (PoP), ball grid array (BGA), etc. Each package type has a different data I/O layout. That is, the mth data bit for a PoP package is not located at the same x-y coordinate as the mth data bit for an MCP package. Thus, a DRAM device that supports memory operations where data bit order is required must account for the data I/O layout of each type of package for which the DRAM device is compatible. Otherwise, DRAM-to-package data bit ordering requirements are forced upon each of the different package types.